Processors and chipsets typically use event signals to inform each other of events. To support event signals, processors and chipsets include pins for sending and receiving the event signals. There are a variety of independent reasons, however, to eliminate or reduce the number of event signals. One reason to eliminate or reduce the number of event signals is to reduce manufacturing costs associated with pins to receive and send event signals. Processors and chipsets tend to be pin-limited due to package or pad constraints. If the die of the processor or chipset is pad limited, then the extra pad results in a direct increase to the die size. Even if the die is core limited, freeing the pad allows the pad to be used for power or ground, and thus improves the package electrical characteristics.
Another reason is that routing of event signals is difficult in uni-processor environments and even more difficult in multi-processor environments. Physical routing of event signal lines often limits the size of the motherboard. Reducing the number of event signals and corresponding event signal lines may help in shrinking board sizes. Yet a further reason for eliminating or reducing event signals is to reduce costs associated with pull-up resistors and the power planes supporting event signals. Because of voltage differences between the chipset and processor, the chipset has typically required external pull-up resistors or an extra power plane to support legacy event signals between the different voltage domains. Removing legacy event signals may save power by eliminating or reducing the number of pull-up resistors or may reduce the number of power planes on the chipset.
A further reason for eliminating event signals is that elimination of these event signals would ease testing. Legacy event signals have typically been asynchronous from the perspective of the processor, because the processor and chipset have used different clock frequencies. The asynchronous nature of the event signals prevents using less costly, deterministic testing techniques to validate the platform.